1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same, and particularly, to a technology employing a fine gate forming process using a sidewall pattern transfer method.
2. Description of the Related Art
In recent years, the performance of a large scale integrated circuit (LSI) formed on a silicon substrate has been significantly increased due to a finer device used for the LSI. In other words, the performance has been improved by reducing, based on a so-called scaling law, a gate length of a metal oxide semiconductor field effect transistor (MOSFET) used for a logic circuit or for a memory device such as a static random access memory (SRAM). Alternatively, the performance may have been improved by thinning a gate insulator.
Among the above, with regard to the reduction of the gate length, it has become more and more difficult to form a fine gate electrode pattern along with changes in generations. In some cases, the gate electrode has become so fine that a resolution limit of optical lithography has already been exceeded. Accordingly, it has become extremely difficult to form a thinner pattern by a conventional combination of resist coating and ultraviolet light exposure and to control a spatial fluctuation of a pattern formed by the above combination.
Therefore, in stead of directly forming a thin gate pattern by using resist, a method has been recently proposed in which: a dummy pattern is first formed; an insulator film, polysilicon, amorphous silicon or the like is deposited onto the dummy pattern; entirely perform reactive ion etching (RIE), which is also called as a sidewall leaving process, to form sidewall portions formed of the deposited film around the sidewalls of the dummy pattern; the dummy pattern is removed thereafter; and a gate electrode or a silicon substrate is processed using the thin sidewall patterns as masks.
For example, a method of processing a silicon substrate by the above method is disclosed in “p. 421, IEDM 2001 Tech. Dig., by Y, -K. Choi, et al.” This method will be hereinafter referred to as a sidewall pattern transfer method. According to this method, the thin pattern formed by the sidewall leaving process is formed basically depending only on the film thickness of the deposited film and an etching condition. In addition, a thin line can be formed even if the fine gate pattern is not formed using resist. In practice, this portion requires a large pattern formation using resist because a contact region for connecting a metal wiring portion with the gate electrode is necessary. However, a thin line pattern of the gate electrode portion to be a channel portion can be formed without using lithography.
Meanwhile, a fin field effect transistor (FinFET), which is one of three dimensional MOSFETs and utilizes as channels side portions of a device region thinly cut out into oblong strips, is described in “p. 1032, IEDM 1998, by D. Hisamoto et al.”
FIG. 29 shows an example of a typical layout of a complementary metal oxide semiconductor (CMOS) inverter (inverter chain) made up of conventional MOSFETs. In this CMOS inverter, a gate electrode region 201 is connected to a drain region 203 of a p-channel MOSFET (pFET), a drain region 202 of an n-channel MOSFET (nFET), and a pad region 209 of a gate electrode. A plurality of source regions 205 of the pFETs and a plurality of source regions 204 of the nFETs are arranged in parallel. Similarly, a plurality of drain regions 202 of the nFETs and a plurality of drain regions 203 of the pFETs are arranged in parallel. A metal wiring 206 supplying a power supply voltage (Vcc) is connected to the source region 205 of the pFET through a pad region 208. Moreover, a metal wiring 207 supplying a ground voltage (Vss) is connected to the source region 204 of the nFET through the pad region 208. In this way, only one gate electrode 201 is disposed in one device region. Here, the pad region 209 of the gate electrode is shared by the nFET and the pFET. It is possible to divide the gate electrode into two separate gate electrodes one of which is for the nFET and one for the pFET, and also possible to connect the separate gate electrodes with the metal wiring 206 and 207, respectively. Further, if a gate length between the adjacent MOSFETs is Lg, a device isolation width 210 is Li, a source region length (channel length direction) is Ls and a drain region length (channel length direction) is Ld, an area occupied by one CMOS inverter is proportional to Li+Ls+Ld+Lg, which determines a pitch between the inverters.
By contrast, FIG. 1 of Japanese Patent Laid-Open Hei 7-202146 (Technical Literature 1) discloses a technology in which a gate electrode encloses a region surrounding a source or drain region in order to suppress a gate resistance increase attributable to a finer gate length in a highly integrated CMOS logic LSI. Here, the gate electrode has an electrically closed loop shape.
However, the gate pattern formed by the sidewall pattern transfer method forms the sidewall portions over the entire dummy pattern. Therefore, the gate electrode here is connected to form a loop shape along the shape of the dummy pattern unlike the conventional straight gate electrode.
Therefore, the gate electrode cannot be formed using the layout of the MOSFET, where the conventional gate electrode structure is employed, as it is. If this layout should be used, a process of processing the gate electrode is further required. Paradoxically, it is clear that, if the shape of the gate electrode formed by the sidewall pattern transfer method is employed as it is, a basic logic circuit such as an inverter cannot be constituted in the layout of the conventional transistor.